Commit 653fd170 authored by aenerine's avatar aenerine
Browse files

Changed Out of Contex for BD to Global

parent 510d4bc3
......@@ -4,7 +4,7 @@
"boundary_crc": "0x55D709A942F40D2A",
"device": "xczu7ev-ffvc1156-2-e",
"name": "Ver_Cntrl_ZynqMPPS",
"synth_flow_mode": "Singular",
"synth_flow_mode": "None",
"tool_version": "2019.1",
"validated": "true"
},
......
......@@ -2,39 +2,11 @@
<Root MajorVersion="0" MinorVersion="37">
<CompositeFile CompositeFileTopName="Ver_Cntrl_ZynqMPPS" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1584912203"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1584912203"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1584912203"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1584912203"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1584913150"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1584913150"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1584913150"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1584913150"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="Ver_Cntrl_ZynqMPPS_sim_netlist.vhdl" Type="VHDL">
<Properties IsEditable="true" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<UsedIn Val="SINGLE_LANGUAGE"/>
</File>
<File Name="Ver_Cntrl_ZynqMPPS_sim_netlist.v" Type="Verilog">
<Properties IsEditable="true" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<UsedIn Val="SINGLE_LANGUAGE"/>
</File>
<File Name="Ver_Cntrl_ZynqMPPS_stub.vhdl" Type="VHDL">
<Properties IsEditable="true" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTH_BLACKBOX_STUB"/>
</File>
<File Name="Ver_Cntrl_ZynqMPPS_stub.v" Type="Verilog">
<Properties IsEditable="true" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTH_BLACKBOX_STUB"/>
</File>
<File Name="Ver_Cntrl_ZynqMPPS.dcp" Type="DCP">
<Properties IsEditable="true" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
</File>
<File Name="ip\Ver_Cntrl_ZynqMPPS_zynq_ultra_ps_e_0_0\Ver_Cntrl_ZynqMPPS_zynq_ultra_ps_e_0_0.xci" Type="IP">
<Instance HierarchyPath="ZYnqMP_PS"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
......
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date : Sun Mar 22 22:27:18 2020
// Host : DESKTOP-G9E3TKK running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// H:/vivado_versioncontrol/IPI-BD/MPSOC_BD/Ver_Cntrl_ZynqMPPS/Ver_Cntrl_ZynqMPPS_stub.v
// Design : Ver_Cntrl_ZynqMPPS
// Purpose : Stub declaration of top-level module interface
// Device : xczu7ev-ffvc1156-2-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module Ver_Cntrl_ZynqMPPS(DMA_AXIS_tdata, DMA_AXIS_tkeep,
DMA_AXIS_tlast, DMA_AXIS_tready, DMA_AXIS_tvalid, M_APB_paddr, M_APB_penable, M_APB_pprot,
M_APB_prdata, M_APB_pready, M_APB_psel, M_APB_pslverr, M_APB_pstrb, M_APB_pwdata,
M_APB_pwrite, PL_Clk_0)
/* synthesis syn_black_box black_box_pad_pin="DMA_AXIS_tdata[31:0],DMA_AXIS_tkeep[3:0],DMA_AXIS_tlast,DMA_AXIS_tready,DMA_AXIS_tvalid,M_APB_paddr[39:0],M_APB_penable,M_APB_pprot[2:0],M_APB_prdata[31:0],M_APB_pready[0:0],M_APB_psel[0:0],M_APB_pslverr[0:0],M_APB_pstrb[3:0],M_APB_pwdata[31:0],M_APB_pwrite,PL_Clk_0" */;
input [31:0]DMA_AXIS_tdata;
input [3:0]DMA_AXIS_tkeep;
input DMA_AXIS_tlast;
output DMA_AXIS_tready;
input DMA_AXIS_tvalid;
output [39:0]M_APB_paddr;
output M_APB_penable;
output [2:0]M_APB_pprot;
input [31:0]M_APB_prdata;
input [0:0]M_APB_pready;
output [0:0]M_APB_psel;
input [0:0]M_APB_pslverr;
output [3:0]M_APB_pstrb;
output [31:0]M_APB_pwdata;
output M_APB_pwrite;
output PL_Clk_0;
endmodule
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date : Sun Mar 22 22:27:18 2020
-- Host : DESKTOP-G9E3TKK running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- H:/vivado_versioncontrol/IPI-BD/MPSOC_BD/Ver_Cntrl_ZynqMPPS/Ver_Cntrl_ZynqMPPS_stub.vhdl
-- Design : Ver_Cntrl_ZynqMPPS
-- Purpose : Stub declaration of top-level module interface
-- Device : xczu7ev-ffvc1156-2-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ver_Cntrl_ZynqMPPS is
Port (
DMA_AXIS_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
DMA_AXIS_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
DMA_AXIS_tlast : in STD_LOGIC;
DMA_AXIS_tready : out STD_LOGIC;
DMA_AXIS_tvalid : in STD_LOGIC;
M_APB_paddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
M_APB_penable : out STD_LOGIC;
M_APB_pprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_APB_prdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_APB_pready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_APB_psel : out STD_LOGIC_VECTOR ( 0 to 0 );
M_APB_pslverr : in STD_LOGIC_VECTOR ( 0 to 0 );
M_APB_pstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_APB_pwdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_APB_pwrite : out STD_LOGIC;
PL_Clk_0 : out STD_LOGIC
);
end Ver_Cntrl_ZynqMPPS;
architecture stub of Ver_Cntrl_ZynqMPPS is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "DMA_AXIS_tdata[31:0],DMA_AXIS_tkeep[3:0],DMA_AXIS_tlast,DMA_AXIS_tready,DMA_AXIS_tvalid,M_APB_paddr[39:0],M_APB_penable,M_APB_pprot[2:0],M_APB_prdata[31:0],M_APB_pready[0:0],M_APB_psel[0:0],M_APB_pslverr[0:0],M_APB_pstrb[3:0],M_APB_pwdata[31:0],M_APB_pwrite,PL_Clk_0";
begin
end;
--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
--Date : Sun Mar 22 22:22:44 2020
--Date : Sun Mar 22 22:39:09 2020
--Host : DESKTOP-G9E3TKK running 64-bit major release (build 9200)
--Command : generate_target Ver_Cntrl_ZynqMPPS_wrapper.bd
--Design : Ver_Cntrl_ZynqMPPS_wrapper
......
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Mar 22 22:23:23 2020" VIVADOVERSION="2019.1">
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Mar 22 22:39:09 2020" VIVADOVERSION="2019.1">
<SYSTEMINFO ARCH="zynquplus" BOARD="xilinx.com:zcu104:part0:1.1" DEVICE="xczu7ev" NAME="Ver_Cntrl_ZynqMPPS" PACKAGE="ffvc1156" SPEEDGRADE="-2"/>
......
--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
--Date : Sun Mar 22 22:22:44 2020
--Date : Sun Mar 22 22:39:09 2020
--Host : DESKTOP-G9E3TKK running 64-bit major release (build 9200)
--Command : generate_target Ver_Cntrl_ZynqMPPS.bd
--Design : Ver_Cntrl_ZynqMPPS
......@@ -1494,7 +1494,7 @@ entity Ver_Cntrl_ZynqMPPS is
PL_Clk_0 : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of Ver_Cntrl_ZynqMPPS : entity is "Ver_Cntrl_ZynqMPPS,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Ver_Cntrl_ZynqMPPS,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=13,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=6,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_BD}";
attribute CORE_GENERATION_INFO of Ver_Cntrl_ZynqMPPS : entity is "Ver_Cntrl_ZynqMPPS,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Ver_Cntrl_ZynqMPPS,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=13,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=6,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of Ver_Cntrl_ZynqMPPS : entity is "Ver_Cntrl_ZynqMPPS.hwdef";
end Ver_Cntrl_ZynqMPPS;
......
--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
--Date : Sun Mar 22 22:22:43 2020
--Date : Sun Mar 22 22:39:09 2020
--Host : DESKTOP-G9E3TKK running 64-bit major release (build 9200)
--Command : generate_target Ver_Cntrl_ZynqMPPS.bd
--Design : Ver_Cntrl_ZynqMPPS
......@@ -1494,7 +1494,7 @@ entity Ver_Cntrl_ZynqMPPS is
PL_Clk_0 : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of Ver_Cntrl_ZynqMPPS : entity is "Ver_Cntrl_ZynqMPPS,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Ver_Cntrl_ZynqMPPS,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=13,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=6,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_BD}";
attribute CORE_GENERATION_INFO of Ver_Cntrl_ZynqMPPS : entity is "Ver_Cntrl_ZynqMPPS,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Ver_Cntrl_ZynqMPPS,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=13,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=6,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of Ver_Cntrl_ZynqMPPS : entity is "Ver_Cntrl_ZynqMPPS.hwdef";
end Ver_Cntrl_ZynqMPPS;
......
......@@ -40,13 +40,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="5"/>
<Option Name="WTModelSimExportSim" Val="5"/>
<Option Name="WTQuestaExportSim" Val="5"/>
<Option Name="WTIesExportSim" Val="5"/>
<Option Name="WTVcsExportSim" Val="5"/>
<Option Name="WTRivieraExportSim" Val="5"/>
<Option Name="WTActivehdlExportSim" Val="5"/>
<Option Name="WTXSimExportSim" Val="6"/>
<Option Name="WTModelSimExportSim" Val="6"/>
<Option Name="WTQuestaExportSim" Val="6"/>
<Option Name="WTIesExportSim" Val="6"/>
<Option Name="WTVcsExportSim" Val="6"/>
<Option Name="WTRivieraExportSim" Val="6"/>
<Option Name="WTActivehdlExportSim" Val="6"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
......@@ -75,6 +75,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../IPI-BD/MPSOC_BD/Ver_Cntrl_ZynqMPPS/Ver_Cntrl_ZynqMPPS.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../RTL_FIles/TOP/Verison_Cntrl_Top.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="Library" Val="work"/>
......@@ -126,19 +132,6 @@
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="Ver_Cntrl_ZynqMPPS" Type="BlockSrcs" RelSrcDir="$PSRCDIR/Ver_Cntrl_ZynqMPPS">
<File Path="$PPRDIR/../IPI-BD/MPSOC_BD/Ver_Cntrl_ZynqMPPS/Ver_Cntrl_ZynqMPPS.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="Ver_Cntrl_ZynqMPPS"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
......@@ -168,17 +161,6 @@
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="Ver_Cntrl_ZynqMPPS_synth_1" Type="Ft3:Synth" SrcSet="Ver_Cntrl_ZynqMPPS" Part="xczu7ev-ffvc1156-2-e" ConstrsSet="Ver_Cntrl_ZynqMPPS" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/Ver_Cntrl_ZynqMPPS_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="Default_Impl" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-e" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="Default_Synth" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
......@@ -195,24 +177,6 @@
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="Ver_Cntrl_ZynqMPPS_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-e" ConstrsSet="Ver_Cntrl_ZynqMPPS" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="Ver_Cntrl_ZynqMPPS_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<Board>
<Jumpers/>
......
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